In the technology of recent advanced high-speed semiconductor devices, use of the gate length of 0.1 μm or less is becoming possible with the progress in the art of ultrafine semiconductor fabrication processes. Generally, operational speed of a semiconductor device is improved with device miniaturization, while there is a need, in such extremely miniaturized semiconductor devices, to reduce the thickness of the gate insulation film thereof with the decrease of the gate length achieved as a result of the device miniaturization.
When the gate length has been reduced to 0.1 μm or less, on the other hand, the thickness of the gate insulation film has to be reduced to 1–2 nm or less when a conventional thermal oxide film is used for the gate insulation film. In such an extremely thin gate insulation film, however, there inevitably arises a problem of increased tunneling current, while such an increased tunneling current causes the problem of large gate leakage current.
In view of the situation noted above, there has been a proposal of using a high-dielectric material (so-called high-K dielectric material) having a much larger specific dielectric constant as compared with a thermal oxide film and thus capable of achieving a small SiO2-equivalent thickness while maintaining a large physical thickness, for the gate insulation film. Such a high-K material includes Ta2O5, Al2O3, ZrO2, HfO2, ZrSiO4, HfSiO4, and the like. By using such a high-K dielectric material, it becomes possible to use the physical thickness of about 4 nm in ultra high-speed semiconductor devices having a gate length of 0.1 μm or less. Thereby, the gate leakage current caused by tunneling effect is successfully suppressed.
In a semiconductor device that uses such a high-K dielectric film for the gate insulation film, it is preferable to form the high-K dielectric film directly on a Si substrate for reducing the SiO2 equivalent thickness of the insulation film. However, in the case the high-K dielectric film is formed directly on the Si substrate, the metal elements in the high-K dielectric film tend to cause diffusion into the Si substrate, and there arises the problem of carrier scattering in the channel region.
From the viewpoint of improving carrier mobility in the channel region, it is preferable to interpose an extremely thin base oxide film having a thickness of 1 nm or less, preferably 0.8 nm or less, most preferably 0.4 nm or less, between the high-K dielectric gate oxide film and the Si substrate. It should be noted that this base oxide film has to be extremely thin. Otherwise, the effect of using the high-K dielectric film for the gate insulation film would be canceled out. Further, such an extremely thin base oxide film has to cover the surface of the Si substrate uniformly, without forming defects such as interface states.
FIG. 1 shows the schematic construction of a high-speed semiconductor device 1 having a high-K dielectric gate insulation film.
Referring to FIG. 1, the semiconductor device 1 is constructed on a silicon substrate 2 and includes a high-K dielectric gate insulation film 4 such as Ta2O5, Al2O3, ZrO2, HfO2, ZrSiO4, HfSiO4, and the like, formed on the silicon substrate 2 via a thin base oxide film 3. Further, a gate electrode 5 is formed on the high-K dielectric gate insulation film 4.
In the semiconductor device 1 of FIG. 1, there is conducted nitrogen (N) doping in the base oxide film 3 within the range that interface flatness is maintained between the silicon substrate 2 and the base oxide film 3, and because of this, the base oxide film 3 has a larger specific dielectric constant as compared with a pure silicon oxide film. Thereby, it becomes possible to reduce the oxide-equivalent thickness of the base oxide film 3 further. By introducing nitrogen into such an extremely thin base oxide film 3 with a thickness of about 1 atomic layer, it becomes possible to improve the mechanical stability at the interface to the high-K dielectric gate insulation film 4 (Lucovisky, G., et al., Appl. Phys. Lett. 74, 2005, 1999).
As explained before, it is preferable that the base oxide film 3 has as small thickness as possible in such a high-speed semiconductor device 1.
In the case of forming such an extremely thin oxide film on a silicon substrate surface, it is not only necessary to remove the native oxide film but also other impurity element, particularly carbon originating from the organic materials in the atmosphere, from the surface of the silicon substrate. When the film formation process is conducted in the state carbon is remaining on the silicon substrate surface, the carbon atoms cause a reaction with the silicon atoms in the silicon substrate and there is formed SiC on the substrate surface. Such Sic forms defect in the oxide film. Further, the silicon substrate surface thus cleaned has to be planarized before the formation of the thin insulation film. Further, in view of the fact that such a cleaned silicon substrate easily undergoes formation of native oxide film or absorbing of organic materials in the air when the substrate is left in the air, it is necessary that such a substrate pre-processing has to be conducted immediately before the substrate processing by way of a single-wafer process.
Conventionally, several technologies are known for planarizing the silicon substrate surface.
For example, there is a known technology of manufacturing a substrate in which the planarization of the substrate surface is achieved by causing to flow a current in an ultra-high vacuum environment. However, such a planarization process requires ultra-high vacuum environment of 10−9–10−10 Torr, and thus, it is difficult to use such a process for a substrate preprocessing process conducted in a mass production line of semiconductor devices. Further, it is difficult to construct a cluster-type semiconductor production apparatus that conducts a single-wafer process by combining the foregoing planarization process in combination with other semiconductor fabrication processes.
Further, there is a known substrate manufacturing technology that conducts so-called denuded-zone (Dz) annealing for a silicon substrate formed by a Czochralski (Cz) growth method or MCz (magnetic-field-applied Czochralski) growth method and containing large amount of interstitial oxygen at the temperature of about 1100° C. and form an intrinsic gettering layer in the silicon substrate (Matsushita Y., et al., Extended Abstracts of the 18th (1986 International) Conference on Solid State Devices and Materials, Tokyo, 1986, pp. 529–532). However, this substrate manufacturing process is, while effective for reducing the defect density of the substrate, not effective for achieving the planarity, particularly the planarity of atomic-layer grade, on the substrate surface. Further, this process requires a high-temperature treatment in an electric furnace and is not suitable for constructing a cluster-type semiconductor production apparatus that conducts a single-wafer process in combination with other semiconductor manufacturing processes.
Further, there is a known substrate manufacturing technology known as Hi-wafer in which a silicon substrate formed by a Czochralski (Cz) process is held for a long time in a hydrogen ambient at a high temperature of 1100–1200° C. for improvement of the quality of the silicon substrate (NIKKEI MICRODEVICES, May, 1993, pp. 63–64). According to this Hi-wafer technology, it becomes possible to reduce the defect density at the silicon substrate surface further as compared with the case of the Cz substrate subjected to the intrinsic gettering process. Further, there is a known technology of planarizing the silicon substrate surface to the degree that atomic layer steps become observable by conducing a thermal annealing process in the hydrogen ambient at the high temperature of about 1100° C. (Yanase, Y., et al., Electro-Chemical Society, Abstract No. 296, 1993, pp. 486). However, this method, also requiring a high-temperature thermal annealing process in an electric furnace, is not suitable for constructing a cluster-type semiconductor production apparatus that conducts a single-wafer processing in combination with other semiconductor manufacturing processes.
Further, there is proposed a so-called RTH process that achieves planarization by treating a silicon substrate in a low-pressure hydrogen ambient (Ono, A., et al., 2001 Symposium on VL SI Technology Digest of Technical Papers, 7A-2, pp. 79–80). However, this substrate preprocessing process, requiring a high-vacuum environment and hydrogen ambient, is not suitable for constructing a cluster-type semiconductor production apparatus in combination with other semiconductor processes.
Thus, while there have been available processes of planarizing a silicon substrate surface to the degree that atomic layer steps become observable, such conventional processes require ultrahigh vacuum environment for thermal annealing process or thermal annealing process in a hydrogen ambient, and it has been difficult to construct a cluster-type semiconductor manufacturing process that conducts a single-wafer process of large-diameter wafers in combination with other semiconductor processes.
As explained previously, such a nearly complete planarization of silicon surface is essential in the fabrication process of ultrahigh-speed semiconductor devices as the preprocessing process when forming a base oxide film with the thickness of 2–3 atomic layers, in advance to the step of forming the high-K dielectric gate insulation film.